At a high-performance computing occasion this month AMD has given a bit extra element in regards to the 3D chip-stacking strategies it’s to mitigate the slowing of Moore’s Law. The multi-chip, or chiplet structure that’s propping up the AMD Ryzen 3000 processors launching this yr seems to solely be a step on the highway in the direction of totally 3D stacked, heterogeneous processor designs.
With the efficiency advantages of course of node shrinks weakening with each new lithography AMD is keenly searching for methods to maintain its merchandise transferring ahead. While the brand new Zen 2 chiplet design is a crucial method for rising the quantity of silicon in a single socket, it’s a trick that’s going to lose its lustre quick.
“That technique of putting more and dies is going to run out pretty quick,” says Forrest Norrod, senior vice chairman and GM of AMD’s datacentre group, “because there’s a physical limit to how many die you can put into a given socket area. We’re already at the point where today’s CPUs, the packages, are pretty darned close to the size of the original iPhone. They’re huge. You can’t get any more area in two dimensions, so what do you have to do? You go up.”
Norrod was talking on the Rice Oil and Gas HPC convention (through Tom’s Hardware) and made the purpose that even combining chiplet design with true 3D stacking isn’t sufficient to maintain issues transferring ever ahead when it comes to efficiency positive factors. AMD sees the necessity to pair such strategies with scalable interconnects, new reminiscence architectures, and new software program frameworks too.
“The only way to do it is by using every way,” says Norrod, “every trick in the book.”
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The downside is that every one the normal strategies we’ve been seeing used to proceed on the Moore’s Law trajectory are beginning to run dry. And the largest methods have been both elevated clock frequency or elevated density scaling.
“You saw a continuous improvement in clock frequency of digital systems for many, many years” explains Norrod. “The soiled little secret within the trade although, during the last ten years that has stopped, and will now be regressing.
“We have actually been peaked at a most frequency, it’s someplace between Three and 4GHz for at the very least datacentre classed techniques. The intractable mixture of reliability constraints, energy constraints, numerous scaling constraints on resistivity of metallic, signifies that as we frequently shrink our processes now we don’t get any extra frequency. Really with this subsequent node, with out doing extraordinary issues, we get much less frequency.”
So if frequency positive factors are slowing down you utilise the shrinking transistors to squeeze ever extra logic into the identical house.
“It’s alright, it’s cool, density will save us,” says Norrod. “We will just throw more transistors at the problem and that’s what we’ve done for the last ten years… we’re throwing more and more cores, cache, etc. at the problem and we’ve got through the last decade by throwing a lot more transistors into each piece of silicon. The bad news is that game is slowing down as well… It’s not quite done yet, but we can see it on the horizon.”
So, as each would-be city planner is aware of, it’s time to start out constructing upwards. And, whereas we’ve already bought GPUs with high-bandwidth reminiscence strapped to the identical die, the long run is about true 3D stacking. AMD isn’t alone in pondering this; Intel introduced its personal Foveros know-how final yr, being launched into the Intel Lakefield CPUs launching this yr.
That’s a chiplet design mixed with stacked CPU/GPU and I/O layers, with a few DRAM strata topping it off. And that’s the route AMD is seeking to go in too.
“We’re going to move to true 3D stacking,” explains Norrod, “where you do put SRAM and DRAM on top of silicon computing components to give even more bandwidth and continue unlocking more and more performance.”
To begin with it’s going to be most essential for reminiscence, and utilizing the interconnects and software program developments to create a coherent pool of reminiscence that may be accessed by CPU and GPU as one.
That’s not going to look in subsequent yr’s Zen 3, anticipated in 2020, that’s trying prefer it’ll be extra of a half-generation replace than a full redesign of the Zen 2 chiplet structure.
Though possibly Zen Three will arrive with heterogeneous chiplets, with CPU and GPU chiplets intermingling in numerous chiplets on the identical package deal. That would give us a complete new form of APU.
But it’s fairly attainable that Zen four would be the subsequent technology structure to see a real 3D stacked processor arriving in AMD type for the primary time, and fairly presumably with a complete new socket design to assist it.
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