Skip to main content

Advertisement

Springer Nature Link
Log in

Design of Ternary Logic Circuits Using GNRFET and RRAM

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

In this paper, the designs of ternary digital circuits are discussed. The ternary logic is a better choice over conventional logics due its extraordinary offers such as high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented in this paper to design the ternary circuits using graphene nanoribbon field effect transistors (GNRFETs) and resistive random access memory (RRAM). The dimer line of graphene nanoribbon (GNR) is used to control the threshold voltage of GNRFETs. The RRAM is used because it has multilevel cell capacity that enables the multiple resistance state storage in a single cell. The ternary logic basic circuits such as standard ternary inverter (STI), NAND and NOR circuits are proposed. In addition, ternary half adder circuit is designed that helps to develop the complex circuits. The HSPICE simulator is utilized for simulating the proposed designs to obtain the performances such as delay, power and power delay product (PDP). Furthermore, the obtained circuit performances are compared with carbon nanotube FETs (CNTFETs)-based and RRAM-based circuits. The comparison results show that the proposed GNRFET and RRAM circuits achieved 46.11% of overall performance improvement over the CNTFET and RRAM circuits. Furthermore, line edge roughness (Pr) effect on the proposed STI and half adder circuit performance is investigated. The delay values are increased, and the power and PDP values are decreased for the higher Pr values. The effect of process, voltage and temperature (PVT) variations on proposed STI and half adder circuits is also performed to analyze the performance. It noticed that the proposed STI and half adder circuits show minimum variation on performance for the PVT variations.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19

Similar content being viewed by others

Availability of Data and Materials

Data can be available on reasonable request.

References

  1. E. Abbasian, M. Gholipour, A variation-aware design for storage cells using Schottky-Barrier-type GNRFETs. J. Comput. Electron. 19, 987–1001 (2020). https://doi.org/10.1007/s10825-020-01529-y

    Article  Google Scholar 

  2. E. Abbasian, M. Gholipour, F. Izadinasab, Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design. Int. J. Circuit Theory Appl. 49(11), 3630–3652 (2021). https://doi.org/10.1002/cta.3108

    Article  Google Scholar 

  3. E. Abbasian, M. Nayeri, A high-speed low-energy one-trit ternary multiplier circuit design in CNTFET technology. ECS J. Solid State Sci. Technol. 12 (2) (2023). https://doi.org/10.1149/2162-8777/acb8d9

  4. E. Abbasian, M. Orouji, S.T. Anvari, A. Asadi, E. Mahmoodi, An ultra-low power and energy-efficient ternary half-adder based on unary operators and two Ternary 3:1 Multiplexers in 32-nm GNRFET technology. Int. J. Circuit Theory Appl. (2023). https://doi.org/10.1002/cta.3667

    Article  Google Scholar 

  5. E. Abbasian, S. Sofimowloodi, A high-performance and energy-efficient ternary multiplier using CNTFETs. Arab. J. Sci. Eng. (2023). https://doi.org/10.1007/s13369-023-07618-x

    Article  Google Scholar 

  6. E. Abbasian, S. Sofimowloodi , A. Sachdeva, Highly-efficient CNTFET-based unbalanced ternary logic gates. ECS J. Solid State Sci. Technol. 12 (3) (2023). https://doi.org/10.1149/2162-8777/acc137

  7. B. Alessandro, F. Gianluca, I. Giuseppe, Strong mobility degradation in ideal graphene nanoribbons due to phonon scattering. Appl. Phys. Lett. 98 (21), 212111 (2011). https://doi.org/10.1063/1.3587627

  8. S. J. Basha, P. Venkatramana, Investigation of crosstalk issues for MWCNT bundled TSVs in ternary logic. ECS J. Solid State Sci. Technol. 11 (3), 031002 (2022). https://doi.org/10.1149/2162-8777/ac5c85

  9. Y.-Y. Chen et al., A SPICE-compatible model of MOS-type graphene nano-ribon field-effect transistors enabling gate- and circuit-level delay and power analysis under process variation. IEEE Trans. Nanotechnol. 14(6), 1068–1082 (2015). https://doi.org/10.1109/TNANO.2015.2469647

    Article  Google Scholar 

  10. X. Cui, M. Xiao, W. Feng, C. Xiaoxin, A synthesis method for logic circuits in RRAM arrays. Sci. China Information Sci. 63 (2020), 209401 . https://doi.org/10.1007/s11432-019-2684-9

  11. X. Cui, M. Xiao, Q. Lin, L. Xiang, Z. Hang, C. Xiaoxin, Design of high-speed logic circuits with four-step RRAM-based logic gates. Circuits Syst. Signal Process. 39, 2822–2840 (2020). https://doi.org/10.1007/s00034-019-01300-0

    Article  Google Scholar 

  12. S.S. Dan, S. Mahapatra, Impact of Energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor—single electron transistor integrated circuits. IET Circuits Devices Syst. 4(5), 449–457 (2010). https://doi.org/10.1049/iet-cds.2009.0341

    Article  Google Scholar 

  13. J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - part i: model of the intrinsic channel region. IEEE Trans. Electron Devices 54, 3186–3194 (2007). https://doi.org/10.1109/TED.2007.909030

    Article  Google Scholar 

  14. J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - Part II: Full device model and circuit performance benchmarking. IEEE Trans. Electron Devices 54, 3195–3205 (2007). https://doi.org/10.1109/TED.2007.909043

    Article  Google Scholar 

  15. B. M. Divya, S. Sunithamani, Design of ternary D-latch using graphene nanoribbon field effect transistor. in 2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN), 1–4 (2019). https://doi.org/10.1109/ViTECoN.2019.8899731

  16. B.M. Divya, S. Sunithamani, Design of ternary logic gates and circuits using GNRFETs. IET Circuits Devices Syst. 14(7), 972–979 (2020). https://doi.org/10.1109/OJNANO.2020.3020567

    Article  Google Scholar 

  17. B. M. Divya, S. Sunithamani, Performance analysis of graphene based field effect transistor in ternary logic: a review, innovations in cyber physical systems, Lecture Notes in Electrical Engineering, 788 (2021). https://doi.org/10.1007/978-981-16-4149-7_54

  18. Electric Tool, available at: https://www.gnu.org/software/electric/

  19. M. Ghadiry, H. Ahmad, C. Wu Yi, A. A. Manaf, New device structures for graphene nanoribbon field effect transistors. Mater. Express, 6 (3), 265–270 (2016). https://doi.org/10.1166/mex.2016.1304

  20. J. Huang, M. Zhu, S. Yang, P. Gupta, W. Zhang, S.M. Rubin, J. He, A physical design tool for carbon nanotube field-effect transistor circuits. ACM J. Emerg. Technol. Comput. Syst. 8(3), 1–20 (2012). https://doi.org/10.1145/2287696.2287708

    Article  Google Scholar 

  21. R.A. Jaber, J.M. Aljaam, B.N. Owaydat, S.A. Al-Maadeed, A. Kassem, A.M. Haidar, Ultra-low energy CNFET-based ternary combinational circuits designs. IEEE Access 9, 115951–115961 (2021). https://doi.org/10.1109/ACCESS.2021.3105577

    Article  Google Scholar 

  22. M.Z. Jahangir, J. Mounika, Design and simulation of an innovative CMOS Ternary 3 To 1 multiplexer and the design of ternary half adder using Ternary 3 To 1 Multiplexer. Microelectron. J. 90, 82–87 (2019). https://doi.org/10.1016/j.mejo.2019.05.007

    Article  Google Scholar 

  23. M. Kameyama, S. Kawahitho, T. Higuchi, A multiplier chip with multiple-valued bidirectional current-mode logic circuits. Computer 21(4), 43–56 (1988). https://doi.org/10.1109/2.50

    Article  Google Scholar 

  24. S.S. Kumar, A. Gangishetty, S. Rasmitha, M. Manasi, High-performance ternary adder using CNTFET. IEEE Trans. Nanotechnol. 16(3), 368–374 (2017). https://doi.org/10.1109/TNANO.2017.2649548

    Article  Google Scholar 

  25. N. Mahdieh, P. Keshavarzian, N. Maryam, Approach for MVL design based on armchair graphene nanoribbon field effect transistor and arithmetic circuits design. Microelectronics J. 92, 104599 (2019). https://doi.org/10.1016/j.mejo.2019.07.017

  26. S. Mei, M. Bosman, K. Shubhakar, N. Raghavan, L. Ming, K. L. Pey, 3D Characterization of hard breakdown in RRAM device. Microelectronic Eng. 216, 111042 (2019). https://doi.org/10.1016/j.mee.2019.111042

  27. A.J. Ramzi, A. Kassem, A.M. El-Hajj, L.A. El-Nimri, A.M. Haidar, High-performance and energy-efficient CNFET-based designs for ternary logic. IEEE Access 7, 93871–93886 (2019). https://doi.org/10.1109/ACCESS.2019.2928251

    Article  Google Scholar 

  28. S. Rani, B. Singh, CNTFET based 4-Trit hybrid ternary adder-subtractor for low power & high-speed applications. SILICON 14, 689–702 (2022). https://doi.org/10.1007/s12633-020-00911

    Article  Google Scholar 

  29. L. Sanna, B. Anil, A.K. Pandit, S. Gupta, S. Mahajan, A review of graphene nanoribbon field-effect transistor structures. J. Electron. Mater. 50, 3169–3186 (2021). https://doi.org/10.1007/s11664-021-08859-y

    Article  Google Scholar 

  30. K. Saurabh, T. Himanshu, R. Nagarajan, Design of a ternary barrel shifter using multiple-valued reversible logic, in 10th IEEE International Conference on Nanotechnology, 1104–1108 (2010). https://doi.org/10.1109/NANO.2010.5697870

  31. T. Sharma, D. Sharma, Energy efficient circuit design of single edge triggered ternary shift registers using CNT technology. IEEE Trans. Nanotechnol. 22, 102–111 (2023). https://doi.org/10.1109/TNANO.2023.3244746

    Article  Google Scholar 

  32. Stanford Nanoelectronics Lab. Stanford-PKU RRAM Model. [Online]. Available: https://nano.stanford.edu/stanford-rram-34.

  33. S. Sunhae, J. Esan, J.J. Won, B. Park, K.K. Rok, Compact design of low power standard ternary inverter based on OFF-state current mechanism using nano-CMOS technology. IEEE Trans. Electron Devices 62(8), 2396–2403 (2015). https://doi.org/10.1109/TED.2015.2445823

    Article  Google Scholar 

  34. K. Supriya, C. A. Johan and C. J. Faquir, Design of ternary logic combinational circuits based on quantum dot Gate FETs. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 21 (5), 793–806 (2013). https://doi.org/10.1109/TVLSI.2012.2198248

  35. Z.S. Tasnim, F.A. Uddin, H.C. Masud, Design of ternary logic and arithmetic circuits using GNRFET. IEEE Open J. Nanotechnol. 1, 77–87 (2020). https://doi.org/10.1109/OJNANO.2020.3020567

    Article  Google Scholar 

  36. F. Zahoor, T.N.Z. Azni, F.A. Khanday, S.A.Z. Murad, Carbon nanotube and resistive random access memory based unbalanced ternary logic gates and basic arithmetic circuits. IEEE Access 8, 104701–104717 (2020). https://doi.org/10.1109/ACCESS.2020.2997809

    Article  Google Scholar 

  37. F. Zahoor, F. A. Hussin, F. A. Khanday, M. R. Ahmad, I. M. Nawi, C. Y. Ooi, F. Z. Rokhani, Carbon nanotube field effect transistor (CNTFET) and Resistive Random Access Memory (RRAM) based ternary combinational logic circuits. Electronics, 10 (1) (2021). https://doi.org/10.3390/electronics10010079

  38. F. Zahoor, F. A. Hussin, T. Z. A. Zulkifli, F. A. Khanday, U. B. Isyaku, A. A. Fida, Resistive Random access memory (RRAM) based unbalanced ternary inverter. Solid State Technol. 63 (6) (2020). https://solidstatetechnology.us/index.php/JSST/article/view/3774

  39. F. Zahoor, T.Z.A. Zulkifli, F.A. Khanday, Resistive random access memory (RRAM): an overview of materials, switching mechanism, performance, multilevel cell (MLC) Storage. Model Appl. Nanoscale Res. Lett. 15(1), 1–26 (2020). https://doi.org/10.1186/s11671-020-03299-9

    Article  Google Scholar 

  40. F. Zahoor, T. Z. A. Zulkifli, F. A. Khanday, A. A. Fida, Low-Power RRAM Device based 1T1R Array Design with CNTFET as Access Device. in Proc. IEEE Student Conf. Res. Develop. (SCOReD), (2019) 280–283. https://doi.org/10.1109/SCORED.2019.8896306

  41. Y. Zhijie, S. Qingyi, J. Zhang, Super tiny nanoscale graphene nanoribbon field-effect transistor. Chin. J. Phys. 59, 572–577 (2019). https://doi.org/10.1016/j.cjph.2019.03.015

    Article  Google Scholar 

Download references

Funding

No funding.

Author information

Authors and Affiliations

  1. Jawaharlal Nehru Technological University Anantapur, Ananthapuramu, India

    Shaik Javid Basha

  2. Sree Vidyanikethan Engineering College, Tirupati, Affiliated to Jawaharlal Nehru Technological University Anantapur, Ananthapuramu, India

    P. Venkatramana

Authors
  1. Shaik Javid Basha
    View author publications

    You can also search for this author inPubMed Google Scholar

  2. P. Venkatramana
    View author publications

    You can also search for this author inPubMed Google Scholar

Contributions

First author worked on concept, methodology, simulation and writing the manuscript, and second author supervised the first author, investigated the simulation results and reviewed the manuscript.

Corresponding author

Correspondence to Shaik Javid Basha.

Ethics declarations

Conflict of interest

No competing interests.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Basha, S.J., Venkatramana, P. Design of Ternary Logic Circuits Using GNRFET and RRAM. Circuits Syst Signal Process 42, 7335–7356 (2023). https://doi.org/10.1007/s00034-023-02445-9

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-023-02445-9

Keywords